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A comment on Why Is My Perfectly Good Shellcode Not Working? Cache Coherency on MIPS and ARM.

Re:Why Is My Perfectly Good Shellcode Not Working? Cache Coh... by classichasclass on Wednesday February 06, 2019 @09:16AM (#19095178)
The same principles probably apply to Power ISA (isync, hwsync, icbi, etc.), and for that matter SPARC. Lots of PowerPC chips still turn up in embedded applications.
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