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A comment on Verilog sources for Western Digital's open source RISC-V core.

Re:Verilog sources for Western Digital's open source RISC-V ... by Rochus on Saturday February 02, 2019 @11:25AM (#19063793)
Great work, many thanks to WD. As far as I see only a subset of the SystemVerilog features is used. Is there a "coding standard" somewhere available specifying this subset with a rationale? Is it mostly to be compatible with Verilator? Is there information available why they used Verilator and how it has proven itself?
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