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A comment on Verilog sources for Western Digital's open source RISC-V core. Parent comment

Re:Verilog sources for Western Digital's open source RISC-V ... by bogomipz on Sunday January 27, 2019 @03:12PM (#19013533)
>"From cursory glance they have operand read bypass and branch prediction."

I'm not familiar with "operand read bypass", is this the same thing as "operand forwarding"? Is this a pipeline optimization? Might you have any link you could share on this?

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Re:Verilog sources for Western Digital's open source RISC-V ... by thesz on Monday January 28, 2019 @07:14AM (#19016877)
It is the same thing. Just different name.
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