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A comment on Verilog sources for Western Digital's open source RISC-V core.

Re:Verilog sources for Western Digital's open source RISC-V ... by zapdrive on Sunday January 27, 2019 @05:09AM (#19011147)
Is this code just for a processor, or an SOC? How is this different from the open source Shakti processor being designed by IIT Chennai?
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