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A comment on Verilog sources for Western Digital's open source RISC-V core. Parent comment

Re:Verilog sources for Western Digital's open source RISC-V ... by sweden on Sunday January 27, 2019 @05:03AM (#19011136)
You are correct. The most difficult part of a design is not the design itself, it's all the documentation and the verification environment around it.

This is a nice gesture but hardware is a bit different than software and dumping a bunch of RTL code is not really useful.

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Re:Verilog sources for Western Digital's open source RISC-V ... by noobiemcfoob on Sunday January 27, 2019 @03:02PM (#19013484)
A full environment that could get you to a blinking LED off of an FPGA would be the complete dump, but I don't see the value in downplaying publishing a bulk of code that all others have hidden behind lock and key.
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