I spent some time with a team building a ML processor based on associative processing. It still has a classical on-die, multi-tier cache system - built entirely in SRAM - but no ALU. It was designed to handle computations entirely in specialized SRAM arrays.

The concept was designed to handle massively parallel computation & minimize off-chip data transfers as much as possible. Still waiting to see how it will do in production.

http://videos.re-work.co/videos/267-in-place-computing-high-...