Porting Alpine Linux to RISC-V

Re:Porting Alpine Linux to RISC-V by jamesaross on Friday December 21, 2018 @09:36AM (#18733515)

I wrote a short paper for HPEC that included some power and performance benchmarks and analysis on the HiFive Unleashed U540 SoC [0]. The SoC isn't open source as some suggest although I believe the core is based on the open source Rocket Chip Generator [1]. It seems the greatest weakness was in the slow memory interface. The details of memory controller and configuration were proprietary when I tried to find out why it wasn't performing well.

[0] http://www.ieee-hpec.org/2018/2018program/index_htm_files/15...

[1] https://github.com/freechipsproject/rocket-chip

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Re:Porting Alpine Linux to RISC-V by drewg123 on Friday December 21, 2018 @09:56AM (#18733623)

From [0] above:

The STREAM benchmark [6] was also compiled and executed, confirming that DRAM performance is limited to less than 1.6 GB/s on this platform. It’s unclear if this is a problem with the cache hierarchy, memory controller, or the configuration of the DDR Controller Control Registers

Wow, that's unspeakably terrible. That's about 10-20% of the b/w one should get from 2400 mem (depending on how many channels the mem controller uses).

I hope this is some simple misconfiguration that can be fixed in firmware or in the kernel.

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Re:Porting Alpine Linux to RISC-V by nickik on Friday December 21, 2018 @11:37AM (#18734408)

The Freedom platform is open and lots of the tilelink interconnect. The xore is based on rocket but they have some internal changes that is not open source jet.

The generated RTL is open but that is of course limited.

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