ECCploit is the first Rowhammer attack to defeat error-correcting code

Re:ECCploit is the first Rowhammer attack to defeat error-co... by kingosticks on Thursday November 22, 2018 @02:59PM (#18512159)

I always assumed that ECC on these high-end systems was done in hardware by the memory controller. And thus there would be no timing side-channel. Is that really not the case?

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Re:ECCploit is the first Rowhammer attack to defeat error-co... by avianes on Friday November 23, 2018 @04:00AM (#18515267)

Hardware implementation does not mean that there is no timing side-channel. Compute ECC takes few cycles. To avoid timing side-channel, you must design hardware for this purpose.

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Re:ECCploit is the first Rowhammer attack to defeat error-co... by kingosticks on Friday November 23, 2018 @04:14AM (#18515313)

Yeh I realised afterwards that at these high clock speeds maybe they do need some extra cycles to do the correction. I don't see why you must do it in hardware to avoid timing side-channels. You just need to provide a constant latency i.e. The cpu ucode does some nops when correction is not necessary.

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Re:ECCploit is the first Rowhammer attack to defeat error-co... by avianes on Friday November 23, 2018 @10:52AM (#18517107)

I mean, as long as your ECC is built directly into the silicon

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Re:ECCploit is the first Rowhammer attack to defeat error-co... by kingosticks on Friday November 23, 2018 @11:01AM (#18517160)

In that case you need to do the exact opposite i.e. avoid the obvious optimisation of returning data early if no correction is required.

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