AMD Discloses Initial Zen 2 Details

Re:AMD Discloses Initial Zen 2 Details by mda on Monday November 19, 2018 @10:57AM (#18487268)

I/O module is not analog, but most of your points still stand, It is mostly for increasing yields and reducing costs. With this separation they are reducing chiplet size quite a bit, so that they will have superlinear cost reduction on 7nm process.

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Re:AMD Discloses Initial Zen 2 Details by rasz on Monday November 19, 2018 @11:37PM (#18491821)

IO is 100% analog. Slew rates, crosstalk, reflections, routing, etc. It is literary called Black Magic in EE community.

Must read "High Speed Digital Design: A Handbook of Black Magic": https://books.google.pl/books/about/High_speed_Digital_Desig...

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Re:AMD Discloses Initial Zen 2 Details by mda on Tuesday November 20, 2018 @02:43AM (#18492387)

I am not sure our definition of analog are same. Are you claiming that gigantic chip shown in the zen 2 picture is an analog chip?

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Re:AMD Discloses Initial Zen 2 Details by rasz on Tuesday November 20, 2018 @02:10PM (#18496710)

Whole CPU is analog, just hidden away under vendor(cadence/mentor/synopsys/etc) supplied RTL IP building blocks (GDS libraries) abstraction whose specification is highly customized to particular fab house. This lets you design logic part of the circuit without getting into analog hell.

The difference between logic part of CPU and IO is in the amount of work spend on RTL vs direct custom layout of geometric structures on the chip.

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