AMD Discloses Initial Zen 2 Details

Re:AMD Discloses Initial Zen 2 Details by snuxoll on Sunday November 18, 2018 @02:47PM (#18482154)

Threadripper’s 4 die variant had to be “neutered” to remain compatible with the TR4 socket without splitting memory bandwidth. The new I/O chiplet would solve that issue entirely, assuming it comes to Threadripper 3.

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Re:AMD Discloses Initial Zen 2 Details by bpye on Sunday November 18, 2018 @04:14PM (#18482570)

I was just thinking this. Yes it'll have half the lanes of EPYC still, okay, but now the lanes will be connected to all the dies equally rather than to just 1/2 the dies. This hopefully means Threadripper 3 can perform almost as well as EPYC with just 1/2 the memory bandwidth - that isn't insignificant but it's a big improvement on Threadripper 2.

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Re:AMD Discloses Initial Zen 2 Details by Tuna-Fish on Monday November 19, 2018 @07:00AM (#18485787)

An interesting point is that TR owners are much more likely to run their RAM at higher, out of JEDEC spec speeds, so the difference can be a lot smaller than 1/2.

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