Re:Intel's New Low: Commissioning Misleading Core I9-9900K B...
by dragontamer on Tuesday October 09, 2018 @10:53AM
(#18176417)
> AVX512 would be 4x AVX2 is 2x, Ryzen fakes AVX2 instructions with multiple SSE instructions.
Not quite. Everything is fake, because everything is encoded into micro-ops first.
Ryzen's internal micro-op engine is 128-bit wide. But it has 4x pipes... each handling 128-bits at a time. So any 256 bit instruction will simply use two-pipes at a time.
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So the 256-bit instruction does in fact, execute at once.
The difference is that Intel has 3-pipelines, each of which can do a 256-bit instruction by itself.
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In effect: Ryzen is 4x128-bit pipelines, with the ability to merge pipelines together to do a 256-bit instruction.
Intel is 3 x 256-bit pipelines, with the ability (on Skylake-X) to merge pipelines together to do a 512-bit instruction
In any case, Intel has wider pipes than Ryzen. Intel Skylake is effectively a 256-bit CPU, while Ryzen is only a 128-bit CPU.
Not quite. Everything is fake, because everything is encoded into micro-ops first.
Ryzen's internal micro-op engine is 128-bit wide. But it has 4x pipes... each handling 128-bits at a time. So any 256 bit instruction will simply use two-pipes at a time.
-------
So the 256-bit instruction does in fact, execute at once.
The difference is that Intel has 3-pipelines, each of which can do a 256-bit instruction by itself.
-------
In effect: Ryzen is 4x128-bit pipelines, with the ability to merge pipelines together to do a 256-bit instruction.
Intel is 3 x 256-bit pipelines, with the ability (on Skylake-X) to merge pipelines together to do a 512-bit instruction
In any case, Intel has wider pipes than Ryzen. Intel Skylake is effectively a 256-bit CPU, while Ryzen is only a 128-bit CPU.