It's a little different though. GPUs have all those registers because they (1) have a desperate need to optimize around pipeline stalls (because a texture read is many times slower than blocking on main memory) and (2) "know" that they have problem areas appropriate to tiny kernels of code that can work efficiently in fixed size register sets. So they arrange that a "context switch" can be done by changing one index register in a hardware scheduler.

They have a bajillion registers because that works to solve the problem they have, not because they're trying to find out "how to use" them. If you had the same amount of die area and a scalar-ish problem, you'd spend it on a traditional cache hierarchy just like CPUs do.