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Re:David Patterson Says It’s Time for New Computer Architect... by crb002 on Monday September 17, 2018 @05:37PM (#18010328)
Massive parallel prefix and reduction operations in RAM. Start with just the MPI standard reduction ops. 1000x faster than Von Neuman bottleneck.
Re:David Patterson Says It’s Time for New Computer Architect... by crb002 on Monday September 17, 2018 @05:42PM (#18010371)
Then an ASIC for sparse matrix multiply. Valiant's reduction of CFG parsing. Massive speedup to parsing workflows, and boon to security by getting rid of hand rolled parsers.
Re:David Patterson Says It’s Time for New Computer Architect... by snaky on Monday September 17, 2018 @05:54PM (#18010469)
> Massive parallel prefix and reduction operations in RAM

Sounds similar to Micron Automata Processor.

Re:David Patterson Says It’s Time for New Computer Architect... by crb002 on Monday September 17, 2018 @09:03PM (#18011528)
Micron's processor in memory doesn't have near the same bandwidth as a processor in memory array geared to doing parallel prefix.