Re:Path to 2 nm May Not Be Worth It
by baybal2 on Monday August 27, 2018 @01:17PM
(#17852809)
No, no, no, there are a lot of situations where you can't sleep the chip.
The "race to sleep" is a misconception long held by software people.
The situation you describe is only true when the part of the chip doing computation is completely off, and is shunted off from power. That's so called deep sleep.
There is a limit to how frequent you can switch the big and complex chip to low power state, as doing so by itself takes some power and computational overhead to keep track of your power use profile.
For many cases, one have to endure leakage and keep working, like when you have to do IO have to keep the chip "on" anyways, and want to utilize your "on" time as much as possible.
A ton of work have been done on power saving strategies like partial device shutdown, shutting down part of registers, trying to operate different parts of the chip at different frequencies to match io wait and processing time, downshifting to more iterative computational paths, and on and on and on
The "race to sleep" is a misconception long held by software people.
The situation you describe is only true when the part of the chip doing computation is completely off, and is shunted off from power. That's so called deep sleep.
There is a limit to how frequent you can switch the big and complex chip to low power state, as doing so by itself takes some power and computational overhead to keep track of your power use profile.
For many cases, one have to endure leakage and keep working, like when you have to do IO have to keep the chip "on" anyways, and want to utilize your "on" time as much as possible.
A ton of work have been done on power saving strategies like partial device shutdown, shutting down part of registers, trying to operate different parts of the chip at different frequencies to match io wait and processing time, downshifting to more iterative computational paths, and on and on and on