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A comment on The MRISC32 – A vector first CPU design.

Re:The MRISC32 – A vector first CPU design by jrk on Friday August 24, 2018 @09:53PM (#17839111)
The RISC V V-extension follows a Cray-style model, and builds on the work with Hwacha to do mixed-precision vectors much more cleanly:

https://pdfs.semanticscholar.org/b9e8/fcf11b662a31cecd5a08d5... https://www.sigarch.org/simd-instructions-considered-harmful...

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Re:The MRISC32 – A vector first CPU design by mbitsnbites on Saturday August 25, 2018 @04:30AM (#17840108)
Yes, I've seen it. It's quite neat. On the other hand it seems more complex to implement in hardware.

In the simplest possible design, the cost of vector support in the MRISC32 is essentially the cost of the register file (i.e. the register memory), since the vector control logic just consists of a few adders and flip-flops, and the scalar execution units can be reused for vector operations.

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