Ask HN: Does anyone have something negative to say about RISC-V?

Re:Ask HN: Does anyone have something negative to say about ... by deepnotderp on Wednesday July 25, 2018 @02:42PM (#17611716)

1. It fully subscribes to the Stanford Orthodox RISC propaganda. (E.g. "RISC is the best, CISC sux ") and this leads to some rather questionable ISA choices, e.g. No condition codes, poor vector instruction implementations, excessive architectural registers, bad code density, too many ISA extensions, lack of exceptions on many things, etc.

The other general point I really dislike is their focus on ISA as if that matters so much compared to uArch.

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Re:Ask HN: Does anyone have something negative to say about ... by nickik on Wednesday July 25, 2018 @03:15PM (#17611975)

> poor vector instruction implementations

All I have heard is that the people who know about vectors absolutely love the extension. Why is your problem with it?

> bad code density

That is just plain false. Its actually extremely good, RV32C and RV64C easily beat every other ISA. Even without the 'C' extension the difference to the other ISA are minimal.

See: https://www.youtube.com/watch?v=Ii_pEXKKYUg

> The other general point I really dislike is their focus on ISA as if that matters so much compared to uArch.

You don't like that the people who are designing an ISA focus on the ISA? That seems an incredible strange argument.

It is well known and the RISC-V people often repeat that ISA don't matter much for performance. That's why it makes 0 sense not to have an open one that is not restricted so that you can have competition and open source implementations.

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