RISC-V is simpler, and easier to implement. Instruction density is very good with the compressed extension, and is applicable to many niches, from in-order low power embedded cores, to high performance out of order desktop CPUs. We can expect marginal improvements over x86 and ARM across the board.

On the other hand, it is not finished. A number of extensions have yet to be frozen, and we're just beginning to see commercial processors (I mean, where the ISA is exposed to the end user. NVIDIA already uses RISC-V internally).