We didn't use any standard tools for the designs described, almost everything was written in the group. I think our experience was that it was less bug-prone than synchronous design (as far as DIGITAL bugs go), but it is harder to ensure that your analog circuits have the expected digital behavior.
https://ieeexplore.ieee.org/document/1652900/
It's from the Proceedings of the IEEE special issue on async:
https://www.researchgate.net/publication/2985481_Special_Iss...
We didn't use any standard tools for the designs described, almost everything was written in the group. I think our experience was that it was less bug-prone than synchronous design (as far as DIGITAL bugs go), but it is harder to ensure that your analog circuits have the expected digital behavior.