https://www.researchgate.net/profile/Jordi_Cortadella/public...

Here's a RTL-level approach:

https://www.ndsu.edu/pubweb/~scotsmit/uncle_async_12.pdf

Here's one for the hybrid Globally-Asynchronous, Locally-Synchronous model:

https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/200502...

On low-level details, here's two on asynchronous synthesis:

https://ieeexplore.ieee.org/document/1327634/

http://orbit.dtu.dk/files/3459606/Behavioral%20Synthesis%20N...

Synthesis and verification together

http://csl.yale.edu/~rajit/ps/invsynth.pdf

And here's a few designs from my collection:

http://vlsi.cornell.edu/~rajit/ps/dram.pdf

https://escholarship.org/uc/item/23n9d4pj

https://pdfs.semanticscholar.org/2c07/66eda008b59750eb1e789f...

Note: That's an earlier one I'm including since older nodes are still available via MOSIS and Europractice. Any patents are probably expired. It got first pass in silicon, too.

And I just randomly found this paper that has an optimization algorithm to reduce the area and latency disadvantages of asynchronous circuits:

http://www.cs.columbia.edu/~cjeong/papers/aspdac07.pdf