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Re:Intel’s High-End Cascade Lake CPUs to Support 3.84 TB of ... by gameswithgo on Tuesday July 17, 2018 @09:28AM (#17549566)
AMD is guilty of it as well. "AVX2" -> not really! But yes I do wish them well. Make the avx support real AMD!
Re:Intel’s High-End Cascade Lake CPUs to Support 3.84 TB of ... by hajile on Tuesday July 17, 2018 @11:25AM (#17550331)
AVX2 is a set of instructions and AMD supports them. How they support them is a different question. Does Intel not support AVX512 because their processors run at a lower clockspeed when they execute? There are more and less efficient ways to support an instruction set.

AMD decided that consistent clockspeeds were more important than wider units. They decided that most users won't use enough AVX instructions to overwhelm the AVX unit (especially with consistent clocks), so there was no justification in ballooning the die size and increasing power consumption without a decent payoff.

https://en.wikipedia.org/wiki/Advanced_Vector_Extensions#New...

Re:Intel’s High-End Cascade Lake CPUs to Support 3.84 TB of ... by cmsimike on Tuesday July 17, 2018 @10:31AM (#17549957)
As far as I know, Ryzen has avx-256, its four 128bit units can join as two 256 bit ones without any penalty.

What makes this not real AVX? Because there is not one dedicated 256-bit unit?

Re:Intel’s High-End Cascade Lake CPUs to Support 3.84 TB of ... by ajross on Tuesday July 17, 2018 @10:57AM (#17550106)
> without any penalty

Except literally running at half capacity. That doesn't qualify as a "penalty" to you?

The point was that AMD advertised support for AVX in a context where you'd expect it to be performance-comparable, and what they shipped was "support" for AVX in the sense that the code wouldn't crash, but wouldn't provide any performance benefit over SSE either.

Re:Intel’s High-End Cascade Lake CPUs to Support 3.84 TB of ... by hajile on Tuesday July 17, 2018 @11:31AM (#17550375)
https://en.wikichip.org/wiki/intel/frequency_behavior

Intel reduces clockspeeds when running AVX2 and drastically decreases clockspeeds when running AVX512. AMD's slightly smaller unit doesn't need to slow down, so the actual performance difference is smaller than it would appear.

Changing frequency takes time. Also, if you are putting through an AVX instruction and a few integer instructions at the same time, the integer instructions will downclock the whole time the AVX pipeline is in use (plus the time before/and after while the clockspeed is being adjusted) decreasing performance for more than just the AVX.

There are a couple articles written on the topic. Here's one.

https://blog.cloudflare.com/on-the-dangers-of-intels-frequen...

https://software.intel.com/en-us/forums/intel-isa-extensions...

Re:Intel’s High-End Cascade Lake CPUs to Support 3.84 TB of ... by Const-me on Tuesday July 17, 2018 @10:24PM (#17555159)
> Except literally running at half capacity.

I’ve been writing SIMD code for some time now, and I disagree.

You can read the documentation I’ve generated https://github.com/Const-me/IntelIntrinsics AVX intrinsics begin with _mm256_.

You’ll find that for some AVX operations, such as _mm256_fmadd_ps, _mm256_adds_epi8, _mm256_blendv_ps, both latency and throughput of Ryzen is equivalent to Skylake. For some others, e.g. _mm256_add_ps, _mm256_mul_ps, Ryzen is close to some older Intel, Haswell or Broadwell. Only for very rarely used stuff, e.g. _mm256_broadcast_ps, _mm256_madd_epi16, Ryzen is significantly slower than Intel.

Re:Intel’s High-End Cascade Lake CPUs to Support 3.84 TB of ... by gameswithgo on Tuesday July 17, 2018 @11:01AM (#17550131)
oh, they are twisting words with the marketing about "no penalty" pretty bad!
Re:Intel’s High-End Cascade Lake CPUs to Support 3.84 TB of ... by gameswithgo on Tuesday July 17, 2018 @10:52AM (#17550075)
> without any penalty.

My understanding is that without any penalty was not true, but it is possible the new gen cpus have changed that, I have not firsthand benchmarked it.