Arm kills off its anti-RISC-V site after own staff revolt

Re:Arm kills off its anti-RISC-V site after own staff revolt by rwmj on Wednesday July 11, 2018 @06:00AM (#17505685)

SiFive's cores are Rocket, which is open source. lowRISC is based on Rocket too. SiFive include proprietary IP for DDR4, ethernet PHY and other things, although I'm pretty sure they'd jump at the chance to replace those bits with open source equivalents if they existed.

As for your claim "I don't think most RISC-V cores are open source" it depends how you define "most", but it's a complicated picture. There are competitive open source cores (Rocket for in-order, BOOM for OoO, Pulpino, PicoRV32).

There are also several completely proprietary designs, as there should be, such as Western Digital's two different 32 bit RV32 core designs which we expect will ship a billion units next year.

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Re:Arm kills off its anti-RISC-V site after own staff revolt by makomk on Wednesday July 11, 2018 @08:55AM (#17506459)

As far as I can tell, SiFive refuse to say what open source code (if any) their commercial cores such as the E31 are based on, or what changes they've made to it if it is based on open source code. See https://forums.sifive.com/t/more-details-for-e31-core/1165 Basically, it's a proprietary blob which you don't know the internals of just like ARM. They've confirmed that U54 and some of their FPGA-only cores are based on Rocket, but those aren't the cores they're offering commercially.

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