Re:ARM: “RISC-V Architecture: Understand the Facts”
by deepnotderp on Monday July 09, 2018 @12:31PM
(#17491447)
Yeah, no shit, because there's no major RISC-V silicon that's OoO. If you solely look at ARM cores that don't speculate, then ARM cores aren't vulnerable either.
Also pretty sure BOOMv2 has been taped out: https://content.riscv.org/wp-content/uploads/2017/12/Wed0936...
Re:ARM: “RISC-V Architecture: Understand the Facts”
by Symmetry on Monday July 09, 2018 @03:04PM
(#17492603)
Well, the A8 was vulnerable despite being in order but it was a mediocre design with an unusually long pipeline for a core of its class. Of course even in order core speculate a little based on predicting branches and their pipeline lengths but there's a very limited window for things to go wrong without going OoO and almost all in order cores can't execute enough dependent instructions to leak data without realizing they took the wrong branch.
Re:ARM: “RISC-V Architecture: Understand the Facts”
by deepnotderp on Monday July 09, 2018 @08:37PM
(#17494552)
Yes, to be more precise, anything doing anything speculative with memory.
Does someone actually make a RISC-V processor with out of order execution? Or is this a "They're going to make one eventually, so they'll have to address Spectre attacks before that happens" problem?