I was curious about this claim so I looked some numbers up. The latest A11 chip has 8MiB of L2 cache. I could only find a small handful of xeon models with 6MiB of cache while almost all of them contain equal or greater amounts of L2 cache. The chip does not have L3 cache so there is nothing to compare here. The A10 has total package cache less than 8MiB (split into L2 and L3). So I'm not sure this is a good explanation of the performance or size difference.

From what I can tell, while cache is still a large portion of the area, GPU die space is quite large now. The CPU performance seems to be due to expanded execution ports leading to more dispatched instructions per cycle, which is generally a good idea as long as one can keep the execution ports fed with a good amount of speculation in other stages of the pipeline.