Re:Intel's 10nm Is Broken, Delayed Until 2019
by dragontamer on Saturday April 28, 2018 @02:38PM
(#16948917)
I'm not really an expert at the VLSI level, I'm simply thinking from a PCB-perspective (and I just know that some of the same issues occur in the smaller chip-level design).
From my understanding: yes, the CMOS inverters will certainly use power. But you can minimize the use of them through some passive techniques.
Looking into the issue more, it does seem like a naive implementation of synchronized clocks can become costly. But at the same time, I'm seeing a number of research papers suggesting that people have been applying transmission-line techniques to the clock distribution problem.
I've always assumed that it was something that was commonly done at the chip level, but apparently not. These papers were published ~2010 or so.
I do have one follow-up question though: I was under the impression that clock trees contain repeaters in the form of CMOS inverters. Wouldn't those have dynamic leakage which the transmission line stuff doesn't account for?