Implementing FizzBuzz on an FPGA

Re:Implementing FizzBuzz on an FPGA by eebynight on Tuesday March 13, 2018 @03:50PM (#16579167)

Your professor seems great so far but pretty silly of him to teach you verilog instead of VHDL. As an EE myself I haven't seen a job description that says verilog over vhdl in a long time. Might want to familiarize yourself with both if you plan to pursue hardware design further.

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Re:Implementing FizzBuzz on an FPGA by TomVDB on Tuesday March 13, 2018 @05:02PM (#16579754)

VHDL is popular in Europe and the US East Coast. Verilog is king on the West Coast.

An an EE who was schooled in VHDL, gave VHDL classes to new hires and was conditioned to look down on Verilog: after moving from Europe to the East Coast and then the West Coast, I eventually saw the error of my ways and I'm very happy to not have to deal with VHDL anymore.

And for the open source crowd: there is a much large body of decent quality open source Verilog tools than there is for VHDL. So as a hobbyist, it's really a nobrainer.

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Re:Implementing FizzBuzz on an FPGA by monocasa on Tuesday March 13, 2018 @05:20PM (#16579920)

I always got more of a VHDL for FPGAs and Verilog for chips kind of vibe. Not that there's anything intrinsic in those languages, just the kinds of industries that ship FPGAs seem to gravitate to a DoD specified language.

And can you elaborate on what you like about Verilog?

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Re:Implementing FizzBuzz on an FPGA by JoachimS on Tuesday March 13, 2018 @05:29PM (#16579999)

That is very strange. Verilog and SystemVerilog totally dominates VHDL across the globe in terms of market share. Including Europe. Esp if you are designing ASICs, but also for FPGAs.

If you are desinging ASICs and use VHDL you will quite likely end up having mixed language RTL design. And after synthesis the netlist will be in Verilog. So any co-simulation between RTL and netlist must support both languages. Which costs extra in licenses.

Other reasons for choosing Verilog is that the tool developers (being mainly in the US) knows Verilog best. If you look at the adaption rate of new language features, Verilog (SystemVerilog) gets much more attention.

VHDL is for some reason considered a good school language. I don't see the point of it. It's a bit like teaching the ISO stack. The industry has chosen another stack, the pedagogical value if ISO vs TCP/IP is slim to none. The same can (imho) be said for VHDL.

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Re:Implementing FizzBuzz on an FPGA by q3k on Tuesday March 13, 2018 @04:17PM (#16579396)

Depends on where you're located. Counter anecdata: I've seen much more EE jobs asking for Verilog than VHDL :).

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Re:Implementing FizzBuzz on an FPGA by dzamlo on Tuesday March 13, 2018 @04:31PM (#16579512)

From what I read, this is very different between the US and Europe.

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Re:Implementing FizzBuzz on an FPGA by pitaj on Tuesday March 13, 2018 @09:01PM (#16581391)

I know Intel uses Verilog.

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Re:Implementing FizzBuzz on an FPGA by smalley on Tuesday March 13, 2018 @11:39PM (#16582084)

The majority of Intel's newly developed HDL is systemVerilog on the design and verification side, but honestly there is still a mix of everything going on there.

Some chip designs make use of purchased IP which is at times VHDL. Heck some unit owners and architects even experimented with HLS (High Level Synthesis) using SystemC for part of the graphics hardware and a few units still have state machines which automatically translate from a DSL or word macros.

I do think both of the trends people are identifying hold true though. US is more verilog than not, Europe I see more VHDL than verilog. US exceptions are typically FPGA developers and defense contractors (but definitely not universally).

In my opinion I find systemVerilog to be much easier to design in with less verbose syntax, better tooling and some nice constructs that make realizing design intent easier. systemVerilog always blows away VHDL in testbench design and general verification environment support. I would never wish designing an elaborate testbench in VHDL on an engineering team. VHDL does have some advantages if you have requirements to do a lot of formal property verification though.

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