Re:Why has CPU frequency ceased to grow? (2014)
by saltcured on Wednesday February 21, 2018 @04:27PM
(#16433133)
Are you aware of previous work on processor-in-memory architecture research? They considered things like this, but I think it stalled out due to semiconductor process and economic practicality.
This article mostly mentions a UC Berkeley effort: https://en.wikipedia.org/wiki/Computational_RAM
This page mentions others: http://www.ai.mit.edu/projects/aries/course/notes/pim.html
Re:Why has CPU frequency ceased to grow? (2014)
by microcolonel on Wednesday February 21, 2018 @09:02AM
(#16429461)
> memory be cleared without zeroes
In some specific cases, such as when the Linux kernel maps memory into your process, this is exactly what happens. When you write the page, it faults and clears it on demand; but I don't think there would be a considerable benefit to doing this at a finer granularity.
Re:Why has CPU frequency ceased to grow? (2014)
by rbanffy on Wednesday February 21, 2018 @09:45AM
(#16429777)
Ideally, you would prefer to postpone the actual writing to memory to the moment the cached version is evicted from on-chip caches. When you write that data to RAM, it'll take a lot of CPU cycles during which even external memory fetches will end up being delayed. And if you want to write all zeros from that page when all you are using are the first 10 bytes, it's a lot of cycles that are going to waste. Being sure the memory was actually zeroed out when you commit those bytes to DDR could save a relatively large time for the memory buses.
Hashing, maybe sorting, blitting and some math could be performed at the on-module DRAM controller level even, without data crossing over the slow DDR4 bus or mangling the CPU caches.
I'd love, in fact, to explore such an architecture in a simulator. What would happen to CPU performance if, say, hashes could be computed without reading the data, memory be cleared without zeroes hitting the bus or some SIMD operations be conducted on the memory.
Edit: clarify the processing could be done on the module side of the memory bus.