How to Design a New Chip on a Budget

Re:How to Design a New Chip on a Budget by anfilt on Tuesday February 06, 2018 @10:53PM (#16322133)

I would stick with VHDL and SystemC. Any tools that could actual synthesize your designs are going to handle VHDL and Verilog.

I do prefer VHDL to verilog. My main reason is Verilog does not make a distinction between variables and other objects. Verilog treats almost everything as if it were an assignment type. Furthermore, variables in verilog are shared by default. VHDL shows how it should be done. There is a clear distinction between signals and variables. Additionally, variables are local by default.

My opinion of course. Although VHDL can be bit more wordy. However, that's least of my worries (wordiness) when designing something. I would rather have clear semantics for me and other people on what the heck is going on.

However, Verilog is just as capable.

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Re:How to Design a New Chip on a Budget by lambda on Tuesday February 06, 2018 @11:57PM (#16322332)

Chisel compiles to Verilog, so you can use that to bridge to other tools for actually synthesizing your designs.

But it brings with it the full flexibility of a general purpose programming language which makes it a lot easier to make parameterizable designs which can be more easily reused.

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Re:How to Design a New Chip on a Budget by tails4e on Wednesday February 07, 2018 @01:35AM (#16322650)

SystemVerilog is much more capable than either verilog or VHDL, and has brought many of the VHDL safety features to make design with it safer by construction, plus more, without the wordiness. Yes you can still write bad code, but any decent hardware flow, or synthesis step will catch basic things like mis-sharing of variables etc. I agree it's a language weakness it's not an issue in practical hardware design. In addition to The design enhancements, the fact it's got pretty powerful verification features makes it my language of choice today, at least among the low level HDLs.

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Re:How to Design a New Chip on a Budget by wtetzner on Wednesday February 07, 2018 @08:36AM (#16324246)

Have you ever tried Bluespec SystemVerilog? I've never done hardware design, but from what I've read, it seems like an improvement over VHDL and Verilog. I'm curious to hear the opinion of someone who's actually done hardware design.

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Re:How to Design a New Chip on a Budget by anfilt on Wednesday February 07, 2018 @12:23PM (#16326173)

It's better than Verilog. It extends the types system, and makes user defined types easier to use. This helps with a lot with a big design with a lot modules acting as a layer of abstraction. The type system is stronger than verilog to some degree, but still is weakly typed to retain backward compatibility. VHDL still has much stronger type checking.

It also supports direct programming interfaces. For instance you have a chip your designing that needs to run software. Your test bench can call that C function to also test some software at the same time. You can also use it to speed up simulations by just modeling the input and output in C for a module. However, I prefer SystemC for this. It's great for behavior level simulation, and also runs quickly. It also is much easier to interface with any software you want to test with the design.

So I prefer SystemC for behavior models, and VHDL for gate level implementation. However, you can't really ignore verilog. Although, that depends where you are working and who you are working with. System Verilog is kinda of in between SystemC and VHDL.

https://preview.ibb.co/hRz8qc/Screen_Shot_2018_02_07_at_9_21...

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