How to Design a New Chip on a Budget

Re:How to Design a New Chip on a Budget by FPGAhacker on Tuesday February 06, 2018 @08:12PM (#16321515)

I would be happy if all my bullet points applied only to cycle accurate sims.

I think the market would create itself with the right ingredients present. I think a high level language, a well defined intermediate representation with an eye toward synthesis but initially just targeting simulation, and a cycle accurate high performance simulator for said intermediate language would be explosive.

(bonus points for writing the sim in WASM, heh)

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Re:How to Design a New Chip on a Budget by dbcurtis on Tuesday February 06, 2018 @09:47PM (#16321885)

WASM? Well, if I'm going to tilt at windmills, I'll use the project to learn Rust while I'm at it.

Explosive? I remain unconvinced. There just aren't enough people doing that kind of work.

I am excited to see progress in open source FPGA fitters. I've always felt those would be hard to do because without access to the performance model, it is hard to do a good job of auto-placement. So that is cool, even though the current open source tool (I forget the name...) only does a few FPGAs.

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Re:How to Design a New Chip on a Budget by exikyut on Thursday February 08, 2018 @08:06AM (#16331816)

If an open source tool exists, people will end up playing with it. That's categorically not the same of closed source tools - as social creatures we want to share what we're doing, so if we can't share that we stumbled on a cool closed-source tool leaked on the internet, what's the point of playing with it?

So there's that.

I would very much like to hear about your progress on this, FWIW.

Also, I'm not sure, but just in case the following things I was reminded of are directly/indirectly useful/helpful (for ideas or parts, or maybe some of the engineers may be interesting to talk to..?)...

- MARSSx86 - a cycle-accurate x86 emulator built on top of QEMU: http://www.marss86.org/~marss86/index.php/Home

- Cling - a C++ interpreter built on top of LLVM's JIT: https://root.cern.ch/cling

There are several cycle-accurate emulators out there, MARSSx86 is the first I discovered. I'm not sure if it's useful.

I'm not entirely sure why I'm mentioning Cling. It used to be based on a custom runtime (and called CINT) that was absolutely massive and was basically its own C++ implementation. Cling is effectively a very small patch/driver on top of LLVM's C++ implementation and its JIT runtime.

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Re:How to Design a New Chip on a Budget by pedroaraujo on Wednesday February 07, 2018 @08:24AM (#16324182)

Why do you think an high level language would be a positive thing? The ones that are currently available generate worse designs than hand written Verilog.

Verilog is still used for a very good reason, it is not because the EDA industry is stuck in time.

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