AFAICT, Coffee Lake has 24 PCI-E lanes, 8 of which are used to connect to the chipset. If they used all remaining 16 for the GPU, then NVMe and thunderbolt connections would have to go through the south bridge, affecting latency and throughput.

Intel doesn't connect to the chipset with PCIe, it does that with DMI.

Coffee Lake only has 16 PCIE lanes on the CPU, 4 DMI Lanes (about equivalent to 4 PCIE 3.0 lanes) which connect to the PCH and 24 PCIE 3.0 lanes coming from the chipset.

I over simplified. DMI is a PCI Express variant. I thought it had increased to 8 lanes in Coffee Lake, but I was mistaken. That makes it even more important to save some of the CPU PCIe lanes for NVMe and thunderbolt.

I guess I would have preferred to see it be a client on QPI and be cache coherent with the rest of the system, rather than using PCI at all, but yeah, that's asking a bit much on this super short timeframe.

It's enough. Even top end discrete cards can't saturate 16x PCI-E 3

I guess I'd like to see much tighter integration between the two chips so that we don't have to write code that avoids the PCI bus at all costs. Today you fit your entire working set into VRAM and don't touch it from the CPU, so it's sort of hard to say "it's not a deal we don't saturate the bus anyway" when that's only because we bend over backwards to not touch the bus in the first place.

I would imagine that they took the best GPU chip they could afford the space and power for, and found that 8 channels was enough for 99% of their customers?

I assume adding more channels takes space, perhaps the GPU would have had to be lower performance to add more channels?

(speculating)

It's not like they had an option, NVIDIA doesn't do semi-customs you either buy their SOCs or their GPUs as a package.

Isn't that the kind of optimizations that you can only make for consoles, where you know that all users have the same hardware?

No, modern GPU APIs give you plenty of control over data layout, and it's the model AMD had been pimping for a while with their 'HSA' push.

I wasn't thinking about technical constraints, but economic ones. The market that would be able to benefit from this kind of optimization would be very limited as a % of PC gamers (which is already a limited market compared to consoles AFAIK).

Could you elaborate what you mean by tighter? Isn't this the whole point MCM designs?

Right, exactly, but this chip is still as far away from a software perspective as a discrete card would be.

I think part of the point is you wont need a GPU (at least that's the idea).

I'm saying that it's using 8x PCI on the package to connect these two chips together, not additional PCI lanes going out to card slots.