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A comment on Robust and Efficient Elimination of Cache and Timing Side Channels (2015). Parent comment

Re:Robust and Efficient Elimination of Cache and Timing Side... by dgoldstein0 on Sunday January 07, 2018 @02:15AM (#16089721)
and that you can poison prediction state (branch predictor / branch target buffer etc) and cache state to force longer periods of processor speculation, leaving more room for unintended side effects.
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