Robust and Efficient Elimination of Cache and Timing Side Channels (2015)

Re:Robust and Efficient Elimination of Cache and Timing Side... by KirinDave on Saturday January 06, 2018 @01:38AM (#16084163)

Consider though: a similar logic has lead us to not flush the cache, and here we are.

Until we have better ways of reasoning about and restricting the code we are running, it isn't going to get prettier. Conservative approaches like this may not be best for every propose, but in hardened code like a hypervisor it might make sense.

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Re:Robust and Efficient Elimination of Cache and Timing Side... by srett on Saturday January 06, 2018 @06:08AM (#16084765)

Isn't the problem rather that we have instructions to control the cache at all? As far as my research goes, things like CLFLUSH were introduced at the same time as SSE2, which was what, the Pentium III era? We were apparently doing fine without them before that, even with 4+ CPU systems.

I'm currently trying to get the spectre.c PoC to work without using CLFLUSH or similar, but it doesn't look too promising yet. Then again, I only started an hour ago and lack the ability to think in those creative and twisted ways that lead to the discovery of this whole issue in the first place.

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Re:Robust and Efficient Elimination of Cache and Timing Side... by jcelerier on Saturday January 06, 2018 @07:22AM (#16084969)

> We were apparently doing fine without them before that

well, feel free to return to using pentium2-like CPUs

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