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Re:“Intel Core 2 bugs will assuredly be exploitable from use... by tedunangst on Thursday January 04, 2018 @11:01PM (#16076412)
Something like adding "Implicit caching occurs when a memory element is made potentially cacheable, although the element may never have been accessed in the normal von Neumann sequence. Implicit caching occurs on the P6 and more recent processor families due to aggressive prefetching, branch prediction, and TLB miss handling." to the developer's manual.

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