You must be kidding. Normal CPU architectures - the RISC ones - don't have funny things like "microcode" (well, true RISCs don't have it for sure). Majority of CPU architectures nowadays are RISCs. Some legacy ones, like x86, are CISC-translated-to-RISC, as this presentation shows. The native RISC code in them is called "microcode".

Oh yes I was just kidding.

Can we assume you must be kidding too when you use the phrase "Normal CPU architectures"?

It's a combination of microcode and hardwired logic that's common now --- hardwired simple instructions, microcoded complex ones.

In the slide during the presentation at the 10:23 minute mark he shows the short decoders under the instruction register and I believe even those simple instructions are all made up of micro-ops that need to be looked up in ROM as well.

The CPU only executes micro ops, but the "vector decoder" is the only one that uses microcode to sequence the ops.