Lately I've been thinking that something inspired by the Belt idea could be applied to making an innovative homebrew 4-bit TTL CPU. The concept is, feed each of the 4 output bits from a 74181 ALU into a separate chain of 74HCT595 shift registers. (Instead of an implicit accumulator, every machine code command would be an implicit push-result-into-belt.) Taking a slice of each parallel data out pin across the shift register lanes, you get a "belt" slot. I.e. the 4 shift register chips' d0's give you ALU out from time t-0, the 4 d1's give you ALU out from t-1, etc. The effect is that instead of an accumulator register, you have 32 bits of ALU output history (or 64 bits or more if you chain more than one 74595 for each bit). Then, having created an ersatz very wide demux, connect all 4x8 or 4x16 lines to a group of 74151 mux's to get back down to 4-bit register bus values - with the capability that different groups of mux's can independently point to any nibble in the history-memory.

Although the same end result could be accomplished without going through a 4x16 "bit matrix" or "crossbar", the setup has some nice properties, particularly for a hobbyist TTL CPU:

* Generating 16 bit address lines and 8 or 16 bit memory-data IO lines could be done by grabbing 2 or 4 nibbles at a time.

* You could drive LED's or a (decoded) hex 7 segment display directly from the bit-matrix lines to see all N history values.

* If you have at least two mux units, the "A" and "B" inputs of the ALU chip could be pointed at different history values.

* The two mux units could be ganged to feed the wider RAM-address and RAM-data registers.

* When doing math or logic on 8, 16, etc. bit values, you wouldn't have to change the register selectors (mux addresses) to change nibbles: the act of pushing the result moves the next operands into position under the "tape head".

That last point means that a fairly simple TTL circuit could flexibly support 4,8,12,16,...,64 bit ALU ops (provided enough 74HCT595s were connected to provide 2x that many bits total). Just set up the initial data and operation, load a TTL counter with the desired number of nibbles, and let 'er rip at the max speed the 74181 can handle.

I call this "The Suspenders" CPU architecture.