http://millcomputing.com/wiki/Architecture
EDIT:
But to summarize:
This is an exposed pipeline VLIW design except that the instructions are variable width so it doesn't really fit in the traditional conception of VLIW. There are a bunch of clever tricks for compressing the instruction stream and minimizing fetch bandwidth. Instead of registers recent results go into a static single assignment mechanism called the belt where the last N results are visible. To better handle memory speculation register contents are essentially wrapped in Maybe monads in a way that cleverly gets around the Itanium's problems with memory speculation. To better handle data pressure new pages can be declared in the cache hierarchy full of zeroes and are only assigned backing DRAM when ejected. The caches all work in terms of virtual addresses, translation to physical only happens at the DRAM interface. The stack is managed in hardware with its own dedicated queue, the Spiller, which will start pushing data to L2 on its own as it starts to fill up. Code for the Mill is first written to something called general assembly which assumes every possible instruction, infinite execution width, etc. A single pass specialization step goes through and performs necessary substitutions when an executable at the dynamic linking stage.
It links to videos with longer explanations.
They did an entire talk on how to translate a switch block into Mill assembly; that talk didn't really introduce any new hardware features, just describe how to use them.