Re:Power9 to the People
by jabl on Wednesday December 06, 2017 @02:17PM
(#15863993)
I think the usual argument is that the decoder is a small fraction of the total transistor count in a high-performance core.
For microcontroller class HW, the x86 ISA might be a crippling disadvantage compared to RISC-V. For a high-performance core, which AFAIK is something like 20-30 million transistors, not so much. The bigger the core, the smaller the advantage of the ISA.
But yes, I don't there is any reason why RISC-V couldn't be used to create a high-performance core competitive with the x86, POWER, ARM of the day. It's just a hugely expensive affair.
For microcontroller class HW, the x86 ISA might be a crippling disadvantage compared to RISC-V. For a high-performance core, which AFAIK is something like 20-30 million transistors, not so much. The bigger the core, the smaller the advantage of the ISA.
But yes, I don't there is any reason why RISC-V couldn't be used to create a high-performance core competitive with the x86, POWER, ARM of the day. It's just a hugely expensive affair.