Western Digital Plans to Ship More Than One Billion RISC-V Cores a Year

Re:Western Digital Plans to Ship More Than One Billion RISC-... by jabl on Wednesday November 29, 2017 @02:26AM (#15805247)

> That, and I'm kind of disappointed everyone has drunk the RISC kool-aid.

Well, the thing is, RISC "won" the "RISC vs. CISC" wars, in the sense that more or less every ISA designed since has been RISC [1]. Of course, CISC also won in the sense that x86 is still around, and Intel is of course fabulously successful. So at least for high-end cores designed with a big budget, the extra decoder complexity doesn't appear to hurt that much. But if you're doing a new ISA from scratch, no need to repeat the mistakes of the past.

Now, one can always hope that something better comes around. I'm not particularly hopeful that stack machines would be it; Forth has been around for how many decades now, if it would be such a good idea I think it would have already made its breakthrough. But there's plenty of research-y stuff out there (I admit to not being very familiar with most of it). Such as asynchronous (clock-less) logic, non-binary (ternary) logic, Mill(?), reversible computing, dataflow architecture, neuromorphic computing, quantum computing, graph reduction machines, and whatnot.

[1] In the sense of

- Load-store architecture

- fixed-length instructions (yes, ARM thumb and RISC-V C slightly break this, but still)

- ISA designed primarily as a compiler target rather than for human ASM programmers.

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Re:Western Digital Plans to Ship More Than One Billion RISC-... by bluddy on Wednesday November 29, 2017 @02:11PM (#15809808)

RISC won fully. Intel decodes its CISC into an internal RISC (micro-ops) in the hardware. And despite years and years of optimizations, they can't reduce their power requirements to ARM levels.

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Re:Western Digital Plans to Ship More Than One Billion RISC-... by jstewartmobile on Wednesday November 29, 2017 @03:14PM (#15810420)

To be fair, Intel's old x86 ISA is kind of a mess, so microcoding everything back down to an internal RISC may have been the only way for them to even keep the thing manageable.

As CISC goes, 680x0 seemed a little saner to me, and it had more registers so you didn't have to go to memory as much. Back when I did MIPS programming, I remember getting more of a boost out of having more registers to work with than I did from the shorter instruction cycles.

So the variables are all very entangled... is the edge due to RISC? register count? 40 years of cruft (in Intel's case)? better compiler support? something else? I just feel like the whole thing deserves a little more investigation...

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Re:Western Digital Plans to Ship More Than One Billion RISC-... by jstewartmobile on Wednesday November 29, 2017 @09:08AM (#15806853)

Like you said ARM and x86, RISC and CISC, are the winners. I just wonder how much of that victory is due to circumstances of the time (like weak late-1980s compilers) and how much was due to clear technical superiority.

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Re:Western Digital Plans to Ship More Than One Billion RISC-... by jabl on Wednesday November 29, 2017 @04:53PM (#15811209)

Well, if you're asking me, I'd say Intel is successful despite the technical shortcomings of the x86 ISA, not due to any technical advantages of it. Intel has the benefit of huge volumes (thanks to x86, yes), and they are very very good at chucking out big silicon wafers economically with low defect rates.

Thanks to those advantages, Intel can overcome the disadvantages of the ISA. Which aren't that big in their main markets, that is relatively high end cores.

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