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Re:Western Digital Plans to Ship More Than One Billion RISC-... by userbinator on Tuesday November 28, 2017 @08:42PM (#15803738)
That, and I'm kind of disappointed everyone has drunk the RISC kool-aid.

Agree completely. One only has to look at the prominence (or lack thereof) of MIPS, the other "pure RISC" architecture, to see that it's not known for being anything other than cheap. Plenty of low-end Chinese routers, phones, tablets, and various Android-running devices use MIPS; and their performance (or once again, lack thereof) is notable. ARMs are, internally, much closer to x86 than MIPS or RISC-V.

That said, there's always a place for cheaper and simpler 32-bit cores in applications like HDD controllers, where high performance and efficiency is not a primary goal.

If you had a language/compiler that took better advantage of a stack architecture, or even a CISC architecture, the performance would probably be just as good if not better.

Stack architectures are pretty easy to generate code for and have a (slight) advantage with code density, but their memory access patterns are hard to optimise for, and they are even harder to make superscalar.

On the other hand, I think a "CISC-V" could become an interesting and possibly quite competitive alternative to x86.

Re:Western Digital Plans to Ship More Than One Billion RISC-... by kogepathic on Wednesday November 29, 2017 @08:59AM (#15806777)
> Plenty of low-end Chinese routers, phones, tablets, and various Android-running devices use MIPS

I don't think MIPS is common in phones or tablets anymore, those have moved on to the low end of ARM.

However, MIPS is still used in many networking devices and was up until recently, also used in set-top boxes (STB) like the kind you get from your cable provider.

> their performance (or once again, lack thereof) is notable

You don't need gobs of CPU performance in networking devices. All the layer 2 packet handling is done in hardware, and for layer 3 routing the MIPS core(s) are powerful enough to offer 100Mbit NAT performance, which is 99% of what home internet users need currently.

Most managed switches today are either using an updated version of the PowerPC 630 or some ancient and low clocked ARM core. [1]

You don't need gigahertz CPUs in these devices because the CPU is only there to run the management OS (typically Linux) which then configures the switching/routing hardware.

> One only has to look at the prominence (or lack thereof) of MIPS

There are billions of MIPS devices out there. Most homes will have one in their WiFi router, and others in their STB. The only reason MIPS isn't "prominent" is because the products aren't advertised as containing a MIPS core, and people don't know it's MIPS.

[1] https://h50146.www5.hpe.com/products/networking/datasheet/4A...

Re:Western Digital Plans to Ship More Than One Billion RISC-... by jstewartmobile on Tuesday November 28, 2017 @09:27PM (#15804018)
I'd figure at least from the perspective of the JVM and the CLR, you'd have less of an impedance mismatch on a stack machine. And with most compiled languages being conceptually very stack-y, I doubt it would hurt there either.

That, and you could save on instruction bandwidth since the operands could be implicit stack offsets instead of having to be specified in the instruction. (I believe Moore's GreenArray chips packed four instructions to the word.)

It might be a dead-end, or there could be some serious potential that is just being overlooked. Everyone is so accustomed to register machines (CISC or RISC) these days that it may be a while before the idea is reevaluated.

edit: Sorry! Just read this back, and realized I just repeated what you wrote in different words.