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Re:IBM Preps Power9 for AI and HPC Launch, Forges Big NUMA Iron by torpcoms on Monday October 23, 2017 @02:34PM (#15535689)
The Zaius/Barreleye systems use the LaGrange chips instead; the quick breakdown I made for wikipedia was:

    Sforza —   50 mm × 50 mm,     4 DDR4, 48 PCIe Lanes, 1 XBus 4B
    Monza —    68.5 mm × 68.5 mm, 8 DDR4, 34 PCIe Lanes, 1 XBus 4B
    LaGrange — 68.5 mm × 68.5 mm, 8 DDR4, 42 PCIe Lanes, 2 XBus 4B
Though I have no idea what XBus is.

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