Re:Intel Gears Up for FPGA Push
by nxmehta on Wednesday October 04, 2017 @01:42AM
(#15398504)
FYI, the toolchain is shit because:
1. The optimization problems that EDA tools have to solve are about as hard as it gets - NP-hard and sigma 2p problems at a massive scale. I'd argue that these are among the hardest optimization problems in modern computer science today.
2. The number of people with the CS + EE training to develop this software is decreasing. Not a lot of people are getting PhDs in EDA anymore, because:
3. Regular software houses (Google, Amazon, etc.) have about 2-3x the comp as EDA companies. Trust me I've seen a lot of incredibly smart EDA people jump to Google and more than double their salary overnight.
I doubt Intel is going to shift the balance here. It's not easy to develop a fast and efficient SP&R flow.
Re:Intel Gears Up for FPGA Push
by gcp on Wednesday October 04, 2017 @09:20AM
(#15400231)
You know, we would all like faster synthesize and P&R cycles, but when people complain about the tooling being shit, that's not what they're complaining about. (Mostly)
1. The optimization problems that EDA tools have to solve are about as hard as it gets - NP-hard and sigma 2p problems at a massive scale. I'd argue that these are among the hardest optimization problems in modern computer science today.
2. The number of people with the CS + EE training to develop this software is decreasing. Not a lot of people are getting PhDs in EDA anymore, because:
3. Regular software houses (Google, Amazon, etc.) have about 2-3x the comp as EDA companies. Trust me I've seen a lot of incredibly smart EDA people jump to Google and more than double their salary overnight.
I doubt Intel is going to shift the balance here. It's not easy to develop a fast and efficient SP&R flow.