I would have said synchronous digital logic requires a clock. Clearly combinational logic does not. The type of design you do is purely dependent on your needs. Asynchronous design is neither good or bad. It's what you need or it isn't.

Here is a perfectly fine, synthesizable parity generator using a non generative for loop (vhdl):

  library ieee;
  use ieee.std_logic_1164.all;
  
  entity for_parity is
    port (input  : in  std_logic_vector (7 downto 0);
          even   : out std_logic;
          odd    : out std_logic);
  end for_parity ;
  
  architecture for_arch of for_parity is
  
    signal even_parity : std_logic;
  
  begin
  
    calc: process (input) is
    variable temp : std_logic;
    begin 
  
      temp := '0';
      for i in 0 to 7 loop
        temp:=temp xor input(i);
      end loop;
  
      even_parity <= temp;
    end process calc;

    even <= even_parity;
    odd  <= (not even_parity);
  end for_arch;

As for the last point, I make extensive use of sequential logic, a concept made possible by delays through transistors, and I can't think of a more confusing thing to say to someone than "it all happens at once" because it does not.