Re:In-Depth View of Wave Computing’s DPU Architecture, Systems
by FullyFunctional on Saturday August 26, 2017 @06:46PM
(#15107887)
The article is [only] a write up of the Hot Chips presentation (I was there). Without a an external validation of the claims it's merely pretty pictures. Iff their claims holds true, then there's some interesting elements here.
This is far from the only data-flow architecture out there (my favorite is the TRIPS instance of EDGE), but so far none have succeeded in the market.
The self-timed part is using NULL Convention Logic (NCL). Wave have dubbed their implementation of this WTL (see https://news.ycombinator.com/item?id=11469749). There are some very interesting questions about exactly how they use this, but it sounds like the synchronization between compute nodes is using NCL, but the compute nodes are conventional synchronous logic, clocked by the completion signal from NCL. That would certainly be an interesting hybrid, but the 6.7 GHz results begs a lot of questions.
This is far from the only data-flow architecture out there (my favorite is the TRIPS instance of EDGE), but so far none have succeeded in the market.
The self-timed part is using NULL Convention Logic (NCL). Wave have dubbed their implementation of this WTL (see https://news.ycombinator.com/item?id=11469749). There are some very interesting questions about exactly how they use this, but it sounds like the synchronization between compute nodes is using NCL, but the compute nodes are conventional synchronous logic, clocked by the completion signal from NCL. That would certainly be an interesting hybrid, but the 6.7 GHz results begs a lot of questions.