Depends what the ASIC does. The bulk of deep learning is still matrix multiplication and scalar operations on matrices. GPUs are, as the name implies, general-purpose. They aren't as optimized as they could be for optimal performance on matrix ops. This is part of what Google is capitalizing on with the TPU.

Further speedups can be gained by going with lower precision ops (eg: float16). A chip specialized for deep learning could support f16 only, which would allow it to have more compute power using less area and less power.

So, in short, there are ways to make ASICs that are more efficient for deep learning while still giving the ASICs flexibility. ASIC doesn't mean there is no programmability.