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A comment on An FPGA-friendly 32-bit RISC-V CPU implementation. Parent comment

Re:An FPGA-friendly 32-bit RISC-V CPU implementation by Dolu on Thursday July 20, 2017 @05:07AM (#14810986)
Cached an uncached memory access are currently staticaly specified by range :

https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s...

From 0xF000000 to 0xFFFFFFFF access will be uncached.

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