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A comment on An FPGA-friendly 32-bit RISC-V CPU implementation. Parent comment

Re:An FPGA-friendly 32-bit RISC-V CPU implementation by femto on Wednesday July 19, 2017 @06:59PM (#14808742)
If there is a licensing problem with AXI, would Wishbone be a viable alternative [1]?

[1] https://en.wikipedia.org/wiki/Wishbone_(computer_bus)

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Re:An FPGA-friendly 32-bit RISC-V CPU implementation by Dolu on Thursday July 20, 2017 @04:49AM (#14810920)
Yes it would be, it is very easy to retarget the CPU to another memory bus.

Then the Wishbone one isn't "perfect" as it can't map memories which have latencies without performance penality. It would be oky for the data bus of the cpu with or without cache, but for the instruction, without instruction cache, peak CPI would be divided by the memory latency.

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