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A comment on An FPGA-friendly 32-bit RISC-V CPU implementation. Parent comment

Re:An FPGA-friendly 32-bit RISC-V CPU implementation by Dolu on Wednesday July 19, 2017 @05:47PM (#14808281)
Yes i agree, would have been more convenent to use the integrated jtag of the FPGA, but i focused on making an universal solution first :)
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