Agile Paging for Efficient Memory Virtualization [pdf]

Posted by ingve on Friday June 30, 2017 @02:45PM
from the research.cs.wisc.edu dept.

( 2 comments | 37 points | on HN )

Re:Agile Paging for Efficient Memory Virtualization [pdf] by crave_ on Friday June 30, 2017 @06:16PM (#14673888)

"Even the TLBs in the recent Intel Skylake processor architecture, cover only 9% of a 256 GB memory."

Isn't that sort of a lot since the TLB is per context anyways?

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Re:Agile Paging for Efficient Memory Virtualization [pdf] by monocasa on Friday June 30, 2017 @08:43PM (#14674555)

The TLB is shared for the whole system. They added ASIDs so you can keep multiple contexts around without flushing the TLB.

It's still not a great comparison though since TLBs are essentially cache. You only need to keep your working set in them.

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