AMD's Future in Servers: New 7000-Series CPUs Launched and EPYC Analysis

Re:AMD's Future in Servers: New 7000-Series CPUs Launched an... by dom0 on Tuesday June 20, 2017 @07:02PM (#14599298)

Hm? L2 is per core. Always has been in a three+ layer architecture.

Zen has 512K L2 per core and 8M L3 per CCX (two CCX per dice). L3 is a victim cache iirc, unlike previous generations where the L3 was inclusive.

Intel usually went with a similar scheme in the last few years, where the L3 is partitioned into slices assigned to cores; accessing the local slice is faster than a non-local slice. Skylake-SP deviates from this (significantly), for better ... or worse.

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Re:AMD's Future in Servers: New 7000-Series CPUs Launched an... by jnordwick on Tuesday June 20, 2017 @09:49PM (#14600041)

L3 is a victim cache? Intels L4 is the victim cache for their inclusive L3. How does that work? And their L2 is basically a buffer between their L1 and L3.

That doesnt make sense to me. I can't find any good info on this.

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Re:AMD's Future in Servers: New 7000-Series CPUs Launched an... by IanCutress on Wednesday June 21, 2017 @01:23AM (#14600868)

Check AnandTech's Zen review and their recent Skylake-X review for the latest details.

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Re:AMD's Future in Servers: New 7000-Series CPUs Launched an... by snovv_crash on Wednesday June 21, 2017 @01:32AM (#14600908)

Sorry, I meant L3 without leaving the CCX.

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