Too much overhead. FPGAs normally have dedicated memory blocks, since making memory out of "normal" logic cells needs way to much space (registers, temporary buffers for single values, ... can often be embedded in the logic design, but not larger blocks of memory)

The synthesis tools even try wery hard to optimize dumb registers away from your design (you typically blow away ~40 gate equivalents for one bit of simple memory implemented by logic cell). While having clock-gated registers makes the design harder to understand and thus is undesirable, another reason why it is undesirable is that it tends to break any such optimizations performed by synthesis toolchain.