Intel releases the last Itanium chip, the 9700

Re:Intel releases the last Itanium chip, the 9700 by userbinator on Saturday May 13, 2017 @11:56AM (#14331561)

With ever wider SIMD units this is actually happening to some extent. With AVX512 (e.g. on KNL) you can do 64 operations (single precision FLOPs) in vector units in the same amount of time as you can do 1 scalar operation

I was talking about code which simply can't be parallelised because it is branchy or has long and unavoidable dependency chains. In those cases using SIMD instructions will only make the code larger (thus more cache-consuming) and arguably more power-consuming too, since 63/64 of those operations aren't contributing anything to the computation.

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Re:Intel releases the last Itanium chip, the 9700 by KenoFischer on Saturday May 13, 2017 @12:31PM (#14331741)

Yes, I understand. What I meant was that you don't want to be running those kinds of codes on a KNL, because the performance is absolutely terrible. Nevertheless, Intel is producing the KNL, so there's now a market for this kind of thing, which may not have been there 15 years ago.

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